Metal oxide semiconductor field effect transistors (MOSFETs) have been traditionally used and widely applied in the semiconductor technologies. Device dimensions are continuously scaled down to achieve high-performance CMOS ULSIs (Ultra-Large Scale Integrations). For such scaled devices, however, parasitics such as RC delay and source/drain series resistance easily degrade the circuit performance. As suggested in the reference M. T. Takagi, et al., in IEDM Tech. Dig. p.455, 1996, the degradion factor of propagation delay on a gate electrode is a strong function of both channel width and gate electrode sheet resistance. Thus, the finite value of gate electrode sheet resistance limits the maximum channel width which can be used in ULSIs.
Self-Aligned Ti Silicide contact source/drain and gate (Ti salicide) process is one of the candidates for low gate electrode sheet resistance and low source/drain resistance. The ultra-short channel MOSFET with self-aligned silicide contact is required for a high-speed circuit. However, as mentioned in M. Ono, et al., in IEDM Tech. Dig., p119, 1993, it is difficult to define the gate length to be below 0.1 .mu.m due to the limitation of current optical lithography.